1. Field of the Invention
This invention relates to circuitry for the protection of electronic devices. In particular, this invention is related to the protection of integrated circuits from electrostatic discharges.
2. Description of the Related Art
The demand for fast electronic circuits necessitates the development and manufacturing of high-speed integrated circuits. To achieve this end, integrated circuit manufacturers rely on advanced processing technologies to build integrated circuit components at an increasingly miniaturized scale. The advantages of fabricating integrated circuits with smaller components are multi-fold. To begin with, a higher degree of integration per unit area can be accomplished with smaller devices. This translates into lower costs to the manufacturer since more functions can be integrated into smaller die sizes. Users are also benefitted as the use of densely packaged integrated circuits substantially eliminates the interconnect costs on a circuit board. However, most important of all is the performance improvement associated with smaller integrated circuit components. Having smaller components on a semiconductor substrate, the parasitic elements are substantially curtailed. These parasitic elements include parasitic capacitors, resistors, and occasionally inductors adhering to the boundaries and junction interfaces of individual semiconductor devices. They impede the propagation of electrical signals, thus slowing down the operational speed of the internal circuits in general. Unfortunately, down-sizing the components on a semiconductor substrate also poses a drawback. Components with larger geometrical sizes are normally more robust in terms of power ratings. Smaller devices on a semiconductor substrate are more vulnerable to damage in the event of inadvertent power surges on the devices. With modern-day processing technologies, Metal Oxide Semiconductor (MOS) devices are designed with thinner gate and field oxides, and bipolar devices are fabricated with shallower junction depths. The power ratings on these devices are much lower than their previous counterparts. In the event of an Electrostatic Discharge (ESD), which may occur during fabrication, assembly, testing, handling, transportation, or field application, integrated circuits built with smaller components are more susceptible to damage.
Various schemes were devised in the past to address the ESD issue. The most commonly used method is the attachment of one or more reverse-biased diodes on the signal pad leading to the protected circuit, such that the ESD breaks down the reverse diode before damage can be incurred in the internal circuits. However, due to the pre-existent doping requirements of the semiconductor substrate for the optimal performance of the internal circuits, these diodes built under the restricted doping requirements usually have a breakdown voltage much higher than the intended level considered to be safe. As a consequence, considerable damage to the internal circuits can result before the ESD reaches the breakdown voltage of these reverse diodes. Moreover, during the clamping action, excessive ohmic drops across these diodes caused by the high on-state resistance further raise the protection voltage level. Such high protection voltage level can cause additional destruction to the internal circuitry that initially survives ESD voltages up to the diode breakdown voltage.
More elaborate schemes were adopted in the past to remedy the aforementioned situation. One approach is to adopt a three-stage circuit to suppress the ESD. The first stage is disposed close to the signal pad and comprises a breakdown-type device as discussed in the previous paragraph, or a thick field oxide MOS transistor having a large geometry. The second stage circuit is a resistor, and the third stage is another breakdown-type device capable of clamping the protected line at a voltage lower than the intended protection voltage level. The first stage circuit is installed to absorb high voltage ESD surges with voltage values higher than the breakdown voltage of the first stage clamping circuit. Both the second stage and third stage circuits are installed to absorb ESD generated transients of smaller amplitudes, which are incapable of breaking down the first stage circuit but could cause damage if left unattended. The second and third stages are also called into duty after the first stage successfully breaks down a high voltage spike but clamps the protected line at the breakdown voltage of the first stage circuit. Second and third stages filter out the residuals afterwards, with the third stage clamping the internal circuit to be protected at a safe voltage level and the second stage dissipating the ESD energy within the potential difference of the breakdown voltages of the first stage and the second stage circuits. An example of such type of protection circuit is disclosed in U.S. Pat. No. 4,605,980 to Hantranft et al., Aug. 12, 1986.
Another type of ESD protection circuit is disclosed in U.S. Pat. No. 4,819,047 to Gilfeather et al., Apr. 4, 1989. In Gilfeather et al., the active conduction regions of the transistors are relied on for the diversion of the excessive charges.
All the aforementioned ESD protection circuits use large-sized components, based on the belief that a larger device can withstand larger ESD voltages. However, these components are mostly lateral devices in which current crosses the boundaries of the implant or diffusion regions laterally, resulting in highly crowded current densities in these boundary areas. ESD failures of semiconductor circuits are mostly a result of damage produced by Joule heating in a confined area. Specifically, accumulated heat generated by an extraordinarily high current density in a localized area with insufficient heat dissipation can damage the semiconductor materials. To aggravate the matter, these large devices carry with them sizable parasitic elements that render them slow in response. Very often, an ESD with a fast rise time can easily cause irreparable damage to the internal circuits to be protected before the ESD protection circuit can react.
A major area of concern is the defect loss of integrated circuits during the production cycle. In the past, the production of integrated circuits included much manual handling. Modern day production facilities are substantially more automated. An example of an ESD generated by a production machine is when a bonding wire or a micro-probe comes into close contact with an integrated circuit which sits on a surface at a different voltage potential. ESD from a human is basically different from a machine such as a wire-bonder, or an automatic test equipment.
In the evaluation and study of human-generated ESD, the simplified Human Body Model (HBM) equivalent circuit is commonly used. The HBM basically includes a charged external capacitor discharging through an external series resistor into the integrated circuit. An example of an occurrence of a human-generated ESD event is when a person after walking across an insulated floor or with insulated footwear, thereby accumulating electrical charges, touches an external lead of the integrated circuit. The accumulated electrical charges convert into an ESD directly inducing into the integrated circuit.
In the case with machine-generated ESD, the Charged Device Model (CDM) is generally adopted. A simplified CDM equivalent circuit comprises an internal capacitance associated with a tribolectrically charged integrated circuit discharging through an external series resistor into the machine. An example of an occurrence of a machine-generated ESD event is when an integrated circuit becomes tribolectrically charged, such that when it slides down the chute of an automated test machine, a corner lead on the integrated circuit contacts a grounded portion of the machine thereby triggering an ESD discharging from the integrated circuit into the test machine. Unlike the series resistance associated with a human which is in the order of hundreds of ohms, the series resistance associated with a machine ranges only within a few ohms or less. As a consequence, the rise time associated with a CDM event into a machine is much faster and can sometimes be less than one nanosecond. The test criteria for the HBM discharge can be found in MIL-STD-883 Method 3015 Electrostatic Discharge Sensitivity Classification first released by the Department of Defense in 1979. There is presently no full consensus on test criteria for the CDM, but the semiconductor industry has generally begun to follow EOS/ESD Standard DS5.3 Sensitivity Testing--Charged Device Model, released by the Electrical Overstress/Electrostatic Discharge Association in 1993.
Integrated circuits designed with ESD protection circuits that have a slow response time would result in unacceptable rejects in present day production processes, and consequently unnecessarily increase production costs.